1. Field of the Invention
The present invention relates generally to microelectronic circuits, and more particularly, to MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) power devices formed by processes with reduced masking steps arranged in optimal sequences.
2. Description of the Related Art
Power semiconductor devices have long been used as replacement for mechanical relays in various applications. Advent in semiconductor technology enables these power devices to operate with high reliability and performance. Modern day instruments, such as fast switching power supplies and high-frequency ballasts, now built at a miniaturized scale, all require the use of power devices with low power consumption and high reliability. Heretofore, fabricating of these power devices have involved a substantial number of manufacturing steps. To highlight the number of masks and the associated steps involved, FIGS. 1A-1R schematically illustrate the conventional process required to fabricate a planar power MOSFET device.
The fabrication process starts with providing a n-type base silicon wafer 4 as shown in FIG. 1A. An epitaxial layer 6 with a predetermined resistivity is then grown atop the base wafer 4 as shown in FIG. 1B. A field oxide layer 8 is thereafter deposited on the top of the epitaxial layer 6. The resultant structure up to this step is shown in FIG. 1C.
A first mask M1, called the active mask, which defines the active circuit area 10 and the termination circuit area 12 is then disposed atop the oxide layer 8 as shown in FIG. 1D. The active mask M1 is a photoresist layer capable of being patterned by the conventional photolithographic process. After proper patterning, using the patterned first mask M1 as a shield, an etching method is employed to define the field oxide layer 8 as shown in FIG. 1D. The field oxide layer 8 delineates the active circuit region 10 away from the scribe line 14 at a distance d as shown in FIG. 1E. The scribe line 14 is a physical cut line separating the semiconductor dies in a finished wafer. The presence of the terminal circuit region 12 buffering the active circuit region 10 from the scribe line 14 is crucial.
In the design of a field-effect transistor, the active circuit region, such as the region 10 shown in FIGS. 1D-1E should never reach the scribe line 14. The crystal structure at the interior portions of the wafer 4, and the subsequent layers built thereon, are normally orderly in nature. However, the same cannot be said of the vicinities adjacent to the scribe line 14, which are usually crowded with sites of highly energetic dangling bondings with unpredictable energy states. No active devices should be built at these sites with the highly unstable characteristics. If active transistor cells are fabricated at these sites, the transistors possibly would be riddled with intolerable leakage current. Worst of all, these sites are normally triggering locations for avalanche breakdown. For these reasons, during the ion implantation process, the patterned field oxide layer 8 (FIG. 1E) provides a layer break which prevents the active circuit region 10 from reaching the scribe line 14. The formation of the field oxide layer 8 necessitates laying of the mask M1 (FIG. 1D) with the associated masking and patterning steps. The method of the present invention provides, inter alia, a novel approach in which the masking and patterning steps associated with the mask M1 are absorbed into other steps.
Reference is now directed back to FIG. 1E. After the removal of the masking layer M1, a layer of thermally grown gate oxide 16 is then grown on the top of the epitaxial layer 6. Thereafter a layer of polysilicon 18 is laid atop the gate oxide layer 16. The resultant structure up to this step is shown in FIG. 1F.
The polysilicon layer 18 needs to be patterned. A second mask M2, called the gate mask, is patterned on the top of the polysilicon layer 18 as shown in FIG. 1G. Using M2 as a shield, the polysilicon layer 18 is etched resulting in a pattern of gate layer 18 above the substrate 4. After the removal of the masking layer M2, the resultant structure is as shown in FIG. 1H.
The method of ion implantation is then employed to form the active body layer 20, and the termination body layer 22. After a proper drive-in process, the active body layer 20 and the terminal body layer 22 are diffused sufficiently deep into the epitaxial layer 6. The resultant structure up to this step is shown in FIG. 1I.
Another layer of photoresist mask M3, called the source mask, is then patterned above the substrate 4 as shown in FIG. 1J. The structure is subject to another step of ion implantation in which the source regions 24 are formed inside the body regions 20 as shown in FIG. 1K.
What follows is the deposition of a layer of phosphosilicate glass (PSG) 26 above the substrate 4 as shown in FIG. 1L. A fourth mask M4, called the contact mask, is patterned atop the PSG layer 26 as shown in FIG. 1M. After proper etching and removal of the photoresist mask M4, the resultant structure up to this step is shown in FIG. 1N.
P-type material, such as boron, is then implanted and diffused into the structure through the patterned PSG layer 26, resulting in contact diffusion layers 28 formed in the body regions 20 as shown in FIG. 10.
The step of metallization follows. A metal layer 30 is deposited atop the structure by the sputtering process as shown in FIG. 1P. A fifth photoresist mask M5, called the metal mask, is then deposited and patterned on the top of the metal layer 30 as shown in FIG. 1Q. The metal layer 30 is thereafter etched through the mask M5. Furthermore, a drain metal layer 32 is deposited on the bottom side of the wafer 4. The resultant structure up to this step is as shown in FIG. 1R.
Not shown in FIGS. 1A-1R is the deposition of another masking step via a sixth mask M6, called the bonding pad mask, for the purpose of exposing selected areas of the metal layer 30 to the bonding wires, after a protective insulating layer (not shown) is deposited atop the metal layer 30.
In the process of fabricating a MOSFET device as depicted above, there are at least 6 photoresist masks, namely, M1-M6 involved. As with other thin-film microelectronic processes, it is always highly desirable to reduce the number of masks with the associated masking and patterning steps. The advantage of reducing the number of masks in the fabrication process is twofold. First, laying a mask on a semiconductor structure in the manufacturing process is relatively expensive, not merely in the cost of the mask itself but rather in the costs of the various patterning and etching steps associated with the mask. Secondly, the more the number of masking and etching steps are involved, the higher is the chance of contamination during fabrication, and consequently lowers the production yield of the final products. Accordingly, the costs saved by reducing a mask in the fabrication process is beyond the prorated basis of simply reducing a mask.
The advent of high resolution photolithography allows semiconductor components to be formed on a semiconductor substrate with ultra fine geometries. As with other semiconductor devices, the trend in fabrication of power MOSFET devices is toward dense integration. The rationale behind the trend is that the denser the integration, the higher is the number of MOSFET cells operating in parallel and consequently lowers the overall the on-state drain-to-source resistance R.sub.DS. Lower drain-to-source resistance R.sub.DS provides the advantages of lower power dissipation and higher frequency response. However, theoretical feasible as it appears, there are technical complications associated with densely integrating a planar MOSFET array.
Reference is now directed to FIG. 2 which shows the countervailing effects of densely integrating a planar MOSFET device. As mentioned before, advanced development in high definition photolithography allows higher device integration. As integration density increases, cell-to-cell separations decrease. As shown in FIG. 2, the R.sub.DS of each cell during the on-state can be approximated by the following algebraic equation: EQU R.sub.DS =R.sub.s +R.sub.ch +R.sub.j +R.sub.d1 +R.sub.d2 (1)
where R.sub.S, R.sub.ch, R.sub.j, R.sub.d1 and R.sub.d2 are the source resistance, the channel resistance, the junction resistance, the drain resistance at the epitaxial region 6, and the drain resistance at the drain contact region 4, respectively, in ohms. The dominant components are the junction resistance R.sub.j and the drain resistance at the epitaxial region R.sub.d1. First, the epitaxial layer 6 is lightly doped and consequently assumes a high resistivity. Moreover, the epitaxial region 6 is a relatively thick layer and therefore extends a longer resistive path. As integration density increases, the diffusion regions, such as the source diffusions 24 and the body diffusions 20 among the MOSFET cells encroach closer and closer toward each other as illustrated by the directions 21 in FIG. 2. As a consequence, during the device-on state, the drain-to-source current I.sub.DS of each cell only has a limited resistive area to pass through. As shown in FIG. 2, basically, the region signified by the reference numeral 34 has to be shared by two cells, namely, MOSFET cell 36 and MOSFET cell 37. As is well known in the art, the smaller the area of the resistive path, the higher is the resistance value. Equally as detrimental is the current crowding effect in the confined region 34 which also plays a dominant role in increasing R.sub.j and R.sub.d1. Accordingly, the advantage gained in pursuing higher density integration can be totally negated by the increase in drain and junction resistances R.sub.d1 and R.sub.j as explained above.
As with any manufacturing processes, in the production of semiconductor devices, the twin goals of high performance and low production costs are always earnestly sought. Very often, satisfying one goal means sacrificing the other. It has been a long-felt need to provide semiconductor manufacturing processes that can simultaneously meet the two goals.